Before memory devices can be delivered to customers, they must be tested to guarantee their functionality. Tests may relate to a number of parameters, such as operation over a range of voltages, temperatures, and frequencies, and a certain guard band may be built into the tests to ensure memory chips will not fail if operated beyond their specifications for short periods of time.
The testing is part of the manufacturing process, and can be quite time consuming. Any reduction in the time that it takes to test memories is a savings in manufacturing cost, and is therefore desirable. Internal timing marginalities are one source of potential failure for memory chips. Unfortunately, parametric timing and voltage deviations induced by noise cannot be controlled reliably. Thus, the internal set up times for addresses are not controllable parameters for memories, including the present generation of semiconductor dynamic random access memories (DRAMs). Especially high density DRAMs require a long signal path that is very susceptible to noise.
To ensure proper operation under conditions in application settings, memory devices are often tested under specific conditions that mimic those expected to occur during operation in particular applications required by customers. Due to slight timing fluctuations, internal timing marginalities of address and control signals can cause sporadic memory device failures during such application testing. With prior art testing it is very time consuming and expensive to test for noise induced functional marginalities. Thus, it would be desirable to facilitate the testing of marginal internal address and control signal setup times and identification of those timing signals which are problematic.